ARCHITECTURE LEVELS
| LEVEL | GATE | DELAY | CYCLE |
IPC
Instructions per cycle
|
ENERGY |
|---|---|---|---|---|---|
| Overture |
14.4K
14,454
|
24 |
25.0K
25,000
|
1.00 |
8.67B
8,672,400,000
|
PROGRAMMING LEVELS
| LEVEL | GATE | DELAY | CYCLE | ENERGY |
|---|---|---|---|---|
| Circumference |
14.4K
14,412
|
88 | 12 |
15.2M
15,219,072
|
| Mod 4 |
14.4K
14,412
|
88 | 5 |
6.34M
6,341,280
|
| Code Breaker |
14.4K
14,412
|
88 | 1,280 |
1.62B
1,623,367,680
|
| The Maze |
14.4K
14,412
|
88 | 1,409 |
1.78B
1,786,972,704
|
COMPONENT LEVELS
| LEVEL | GATE | DELAY | ENERGY |
|---|---|---|---|
| NOT Gate |
1
|
1
|
1
|
| XOR Gate |
3
|
2
|
6
|
| Bigger OR Gate |
2
|
2
|
4
|
| Bigger AND Gate |
2
|
2
|
4
|
| XNOR Gate |
4
|
3
|
12
|
| Half Adder |
4
|
2
|
8
|
| Full Adder |
9
|
4
|
36
|
| Bit Inverter |
4
|
3
|
12
|
| Byte NOT |
8
|
1
|
8
|
| Byte NAND |
8
|
1
|
8
|
| Adding Bytes |
72
|
32
|
2,304
|
| Multiplexer |
33
|
2
|
66
|
| Saving Gracefully |
10
|
5
|
50
|
| Signed Negator |
96
|
49
|
4,704
|
| Saving Bytes |
80
|
5
|
400
|
| Counter |
201
|
55
|
11.0K
11,055
|
| 1 Bit Decoder |
1
|
1
|
1
|
| 2 Bit Decoder |
6
|
2
|
12
|
| 3 Bit Decoder |
28
|
4
|
112
|
| Little Box |
442
|
6
|
2,652
|
| Arithmetic Logic Unit (ALU) 1 |
132
|
4
|
528
|
| Arithmetic Logic Unit (ALU) 2 |
411
412
|
85
66
|
34.9K
34,935
27.1K
27,192
|
| Conditions |
55
|
8
|
440
|
| Punchcard Programming |
14.4K
14,412
|
88
|
1.26M
1,268,256
|
| Assembly Programming |
14.4K
14,412
|
88
|
1.26M
1,268,256
|
| Byte Constant |
0
|
0
|
0
|
| Byte XOR |
24
|
2
|
48
|
| Equality |
31
|
5
|
155
|
| Unsigned Less |
81
|
34
|
2,754
|
| Signed Less |
96
|
17
|
1,632
|
| LSR |
99
|
6
|
594
|
| Count leading zeroes |
403
|
96
|
38.6K
38,688
|
| ASR |
99
|
6
|
594
|
| One hot encoding |
99
|
6
|
594
|
| Comparison Flags |
1,063
|
72
|
76.5K
76,536
|
| Symphony ALU |
4,817
5,121
|
258
137
|
1.24M
1,242,786
701K
701,577
|
| Condition Match |
11
|
5
|
55
|
| Objective beauty |
31
|
9
|
279
|
