ARCHITECTURE LEVELS
| LEVEL | GATE | DELAY | CYCLE |
IPC
Instructions per cycle
|
ENERGY |
|---|---|---|---|---|---|
| Overture |
14.1K
14,160
|
28 |
25.0K
25,000
|
1.00 |
9.91B
9,912,000,000
|
PROGRAMMING LEVELS
| LEVEL | GATE | DELAY | CYCLE | ENERGY |
|---|---|---|---|---|
| Circumference | 79 | 7 | 1 | 553 |
| Mod 4 | 0 | 0 | 1 | 0 |
| Delicious order | 2,939 | 25 | 49 |
3.60M
3,600,275
|
| Tower of Hanoi |
1.82B
1,828,735,817
|
106 | 1,009 |
195T
195,590,610,571,418
|
COMPONENT LEVELS
| LEVEL | GATE | DELAY | ENERGY |
|---|---|---|---|
| NOT Gate |
1
|
1
|
1
|
| XOR Gate |
3
|
2
|
6
|
| Bigger OR Gate |
2
|
2
|
4
|
| Bigger AND Gate |
2
|
2
|
4
|
| XNOR Gate |
3
|
2
|
6
|
| Half Adder |
3
|
2
|
6
|
| Full Adder |
7
|
4
|
28
|
| Bit Inverter |
3
|
2
|
6
|
| Byte NOT |
8
|
1
|
8
|
| Byte NAND |
8
|
1
|
8
|
| Adding Bytes |
56
64
97
128
132
|
32
17
10
7
6
|
1,792
1,088
970
896
792
|
| Multiplexer |
33
|
2
|
66
|
| Saving Gracefully |
10
|
5
|
50
|
| Signed Negator |
39
|
6
|
234
|
| Saving Bytes |
73
|
5
|
365
|
| Counter |
104
|
10
|
1,040
|
| 1 Bit Decoder |
1
|
1
|
1
|
| 2 Bit Decoder |
4
|
2
|
8
|
| 3 Bit Decoder |
14
|
3
|
42
|
| Little Box |
368
|
5
|
1,840
|
| Arithmetic Logic Unit (ALU) 1 |
64
73
100
|
5
4
3
|
320
292
300
|
| Arithmetic Logic Unit (ALU) 2 |
185
227
253
|
20
14
9
|
3,700
3,178
2,277
|
| Conditions |
13
16
23
50
|
7
6
5
4
|
91
96
115
200
|
| Byte Constant |
0
|
0
|
0
|
| Byte XOR |
24
|
2
|
48
|
| Equality |
31
38
|
5
4
|
155
152
|
| Count leading zeroes |
28
32
|
5
4
|
140
128
|
| Condition Match |
8
12
|
5
4
|
40
48
|
| Objective Beauty |
29
|
5
|
145
|
| Multiply |
480
|
58
|
27.8K
27,840
|
