ARCHITECTURE LEVELS
| LEVEL | GATE | DELAY | CYCLE |
IPC
Instructions per cycle
|
ENERGY |
|---|---|---|---|---|---|
| Overture |
14.6K
14,622
|
108 |
25.0K
25,000
|
1.00 |
39.4B
39,479,400,000
|
PROGRAMMING LEVELS
| LEVEL | GATE | DELAY | CYCLE | ENERGY |
|---|---|---|---|---|
| Circumference |
14.7K
14,702
|
124 | 12 |
21.8M
21,876,576
|
| Mod 4 |
14.7K
14,702
|
124 | 5 |
9.11M
9,115,240
|
| Code Breaker |
14.7K
14,702
|
124 | 2,454 |
4.47B
4,473,759,792
|
| The Maze |
14.7K
14,702
|
124 | 2,432 |
4.43B
4,433,652,736
|
COMPONENT LEVELS
| LEVEL | GATE | DELAY | ENERGY |
|---|---|---|---|
| NOT Gate |
1
|
1
|
1
|
| XOR Gate |
3
|
2
|
6
|
| Bigger OR Gate |
2
|
2
|
4
|
| Bigger AND Gate |
2
|
2
|
4
|
| XNOR Gate |
3
|
2
|
6
|
| Half Adder |
4
|
2
|
8
|
| Full Adder |
9
|
4
|
36
|
| Bit Inverter |
5
|
3
|
15
|
| Byte NOT |
8
|
1
|
8
|
| Byte NAND |
8
|
1
|
8
|
| Adding Bytes |
72
|
32
|
2,304
|
| Multiplexer |
33
|
2
|
66
|
| Saving Gracefully |
10
|
5
|
50
|
| Signed Negator |
96
|
33
|
3,168
|
| Saving Bytes |
80
|
5
|
400
|
| Counter |
193
|
53
|
10.2K
10,229
|
| 1 Bit Decoder |
1
|
1
|
1
|
| 2 Bit Decoder |
6
|
2
|
12
|
| 3 Bit Decoder |
22
|
4
|
88
|
| Arithmetic Logic Unit (ALU) 2 |
484
|
100
|
48.4K
48,400
|
| Conditions |
50
|
7
|
350
|
| Punchcard Programming |
14.7K
14,702
|
124
|
1.82M
1,823,048
|
| Assembly Programming |
14.7K
14,702
|
124
|
1.82M
1,823,048
|
| Byte Constant |
0
|
0
|
0
|
| Byte XOR |
40
|
3
|
120
|
| Equality |
55
|
8
|
440
|
| Unsigned Less |
72
|
11
|
792
|
| Signed Less |
82
|
12
|
984
|
| LSR |
150
|
5
|
750
|
| Count leading zeroes |
300
|
108
|
32.4K
32,400
|
| ASR |
155
|
5
|
775
|
| One-hot Encoding |
150
|
5
|
750
|
| Comparison Flags |
1,056
|
52
|
54.9K
54,912
|
| Symphony ALU |
6,047
|
140
|
846K
846,580
|
| Condition Match |
10
|
6
|
60
|
| Objective Beauty |
28
|
8
|
224
|
| Divide |
5,384
|
536
|
2.88M
2,885,824
|
| Modulo |
7,874
|
978
|
7.70M
7,700,772
|
| Multiply |
2,154
|
343
|
738K
738,822
|
