ARCHITECTURE LEVELS
| LEVEL | GATE | DELAY | CYCLE |
IPC
Instructions per cycle
|
ENERGY |
|---|---|---|---|---|---|
| Overture | 2,295 | 40 |
28.5K
28,587
|
0.87 |
2.62B
2,624,286,600
|
PROGRAMMING LEVELS
| LEVEL | GATE | DELAY | CYCLE | ENERGY |
|---|---|---|---|---|
| Nim |
1.82B
1,828,739,970
|
157 | 7 |
2.00T
2,009,785,227,030
|
| Random Number Generator |
1.82B
1,828,739,970
|
157 | 520 |
149T
149,298,331,150,800
|
| Delicious order |
1.82B
1,828,739,970
|
157 | 1,454 |
417T
417,461,102,871,660
|
| Capitalize |
1.82B
1,828,739,970
|
157 | 617 |
177T
177,148,212,153,930
|
| Tower of Hanoi |
1.82B
1,828,739,970
|
157 | 155 |
44.5T
44,502,387,169,950
|
COMPONENT LEVELS
| LEVEL | GATE | DELAY | ENERGY |
|---|---|---|---|
| NOT Gate |
1
|
1
|
1
|
| XOR Gate |
3
|
2
|
6
|
| Bigger OR Gate |
2
|
2
|
4
|
| Bigger AND Gate |
2
|
2
|
4
|
| XNOR Gate |
3
|
2
|
6
|
| Half Adder |
5
|
3
|
15
|
| Full Adder |
9
|
4
|
36
|
| Bit Inverter |
4
|
3
|
12
|
| Byte NOT |
8
|
1
|
8
|
| Byte NAND |
8
|
1
|
8
|
| Adding Bytes |
88
162
|
32
17
|
2,816
2,754
|
| Multiplexer |
33
|
2
|
66
|
| Saving Gracefully |
10
|
5
|
50
|
| Signed Negator |
96
|
33
|
3,168
|
| Saving Bytes |
80
|
5
|
400
|
| Counter |
141
|
15
|
2,115
|
| 1 Bit Decoder |
1
|
1
|
1
|
| 2 Bit Decoder |
13
|
5
|
65
|
| 3 Bit Decoder |
58
|
6
|
348
|
| Little Box |
480
|
8
|
3,840
|
| Arithmetic Logic Unit (ALU) 1 |
100
|
3
|
300
|
| Arithmetic Logic Unit (ALU) 2 |
394
|
34
|
13.3K
13,396
|
| Conditions |
88
|
7
|
616
|
| Equality |
31
|
6
|
186
|
| Unsigned Less |
57
|
12
|
684
|
| Signed Less |
75
|
13
|
975
|
| Comparison Flags |
713
|
52
|
37.0K
37,076
|
| Symphony ALU |
7,887
|
130
|
1.02M
1,025,310
|
| Objective Beauty |
28
|
8
|
224
|
