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FenixAuriga
COMPLETE 94%

ARCHITECTURE LEVELS

LEVEL GATE DELAY CYCLE
IPC Instructions per cycle
ENERGY
Overture
14.4K 14,409
104
25.0K 25,000
1.00
37.4B 37,463,400,000

PROGRAMMING LEVELS

LEVEL GATE DELAY CYCLE ENERGY
Circumference
14.4K 14,445
120 12
20.8M 20,800,800
Mod 4
14.4K 14,446
120 5
8.66M 8,667,600
Code Breaker
14.4K 14,446
120 296
513M 513,121,920
The Maze
14.4K 14,446
120 1,430
2.47B 2,478,933,600

COMPONENT LEVELS

LEVEL GATE DELAY ENERGY
NOT Gate
1
1
1
XOR Gate
3
2
6
Bigger OR Gate
2
2
4
Bigger AND Gate
2
2
4
XNOR Gate
3
2
6
Half Adder
3
2
6
Full Adder
9
4
36
Bit Inverter
4
3
12
Byte NOT
8
1
8
Byte NAND
8
1
8
Adding Bytes
72
212
32
11
2,304
2,332
Multiplexer
33
2
66
Saving Gracefully
10
5
50
Signed Negator
39
10
390
Saving Bytes
80
5
400
Counter
185
55
10.1K 10,175
1 Bit Decoder
1
1
1
2 Bit Decoder
4
2
8
3 Bit Decoder
24
4
96
Little Box
447
10
4,470
Arithmetic Logic Unit (ALU) 1
116
4
464
Arithmetic Logic Unit (ALU) 2
332
38
12.6K 12,616
Conditions
18
11
198
Punchcard Programming
14.4K 14,445
120
1.73M 1,733,400
Assembly Programming
14.4K 14,445
120
1.73M 1,733,400
Byte Constant
0
0
0
Byte XOR
32
3
96
Equality
47
8
376
Unsigned Less
74
12
888
Signed Less
87
15
1,305
LSR
231
6
1,386
Count leading zeroes
264
16
4,224
ASR
233
7
1,631
One-hot Encoding
231
6
1,386
Comparison Flags
945
1,065
136
17
128K 128,520
18.1K 18,105
Symphony ALU
6,948
7,668
135
41
937K 937,980
314K 314,388
Condition Match
11
5
55
Objective Beauty
31
9
279
Divide
836
133
111K 111,188
Modulo
836
135
112K 112,860
Multiply
1,910
63
120K 120,330