ARCHITECTURE LEVELS
| LEVEL | GATE | DELAY | CYCLE |
IPC
Instructions per cycle
|
ENERGY |
|---|---|---|---|---|---|
| Overture |
15.7K
15,764
|
73 |
25.0K
25,000
|
1.00 |
28.7B
28,769,300,000
|
PROGRAMMING LEVELS
| LEVEL | GATE | DELAY | CYCLE | ENERGY |
|---|---|---|---|---|
| Nim |
1.82B
1,828,739,547
|
167 | 7 |
2.13T
2,137,796,530,443
|
| Random Number Generator |
1.82B
1,828,739,547
|
167 | 520 |
158T
158,807,742,261,480
|
| Delicious order |
1.82B
1,828,739,547
|
167 | 1,487 |
454T
454,129,062,966,963
|
| Capitalize |
1.82B
1,828,739,547
|
167 | 522 |
159T
159,418,541,270,178
|
| Tower of Hanoi |
1.82B
1,828,739,547
|
167 | 1,138 |
347T
347,544,635,949,162
|
COMPONENT LEVELS
| LEVEL | GATE | DELAY | ENERGY |
|---|---|---|---|
| NOT Gate |
1
|
1
|
1
|
| XOR Gate |
3
|
2
|
6
|
| Bigger OR Gate |
2
|
2
|
4
|
| Bigger AND Gate |
2
|
2
|
4
|
| XNOR Gate |
4
|
3
|
12
|
| Half Adder |
4
|
2
|
8
|
| Full Adder |
11
|
4
|
44
|
| Bit Inverter |
3
|
2
|
6
|
| Byte NOT |
8
|
1
|
8
|
| Byte NAND |
8
|
1
|
8
|
| Adding Bytes |
88
|
32
|
2,816
|
| Multiplexer |
33
|
2
|
66
|
| Saving Gracefully |
38
|
6
|
228
|
| Signed Negator |
96
|
33
|
3,168
|
| Saving Bytes |
304
|
6
|
1,824
|
| Counter |
161
|
37
|
5,957
|
| 1 Bit Decoder |
1
|
1
|
1
|
| 2 Bit Decoder |
6
|
2
|
12
|
| 3 Bit Decoder |
28
|
4
|
112
|
| Little Box |
1,308
|
8
|
10.4K
10,464
|
| Arithmetic Logic Unit (ALU) 1 |
148
|
4
|
592
|
| Arithmetic Logic Unit (ALU) 2 |
476
|
66
|
31.4K
31,416
|
| Conditions |
55
|
8
|
440
|
| Byte Constant |
0
|
0
|
0
|
| Byte XOR |
24
|
2
|
48
|
| Equality |
31
|
5
|
155
|
| Unsigned Less |
64
|
13
|
832
|
| Signed Less |
72
|
14
|
1,008
|
| LSR |
99
|
6
|
594
|
| Count leading zeroes |
264
|
16
|
4,224
|
| ASR |
99
|
6
|
594
|
| One-hot Encoding |
99
|
6
|
594
|
| Comparison Flags |
730
|
56
|
40.8K
40,880
|
| Symphony ALU |
4,623
|
130
|
600K
600,990
|
| Condition Match |
8
|
5
|
40
|
| Objective Beauty |
28
|
8
|
224
|
