ARCHITECTURE LEVELS
| LEVEL | GATE | DELAY | CYCLE |
IPC
Instructions per cycle
|
ENERGY |
|---|---|---|---|---|---|
| Overture |
14.1K
14,190
|
83 |
25.0K
25,000
|
1.00 |
29.4B
29,444,250,000
|
PROGRAMMING LEVELS
| LEVEL | GATE | DELAY | CYCLE | ENERGY |
|---|---|---|---|---|
| Circumference |
14.2K
14,256
|
83 | 9 |
10.6M
10,649,232
|
| Mod 4 |
14.2K
14,256
|
83 | 5 |
5.91M
5,916,240
|
| Code Breaker |
14.2K
14,256
|
83 | 436 |
515M
515,896,128
|
| The Maze |
14.2K
14,256
|
83 | 1,626 |
1.92B
1,923,961,248
|
| Nim |
37.5K
37,561
|
147 | 14 |
77.3M
77,300,538
|
| Random Number Generator |
37.5K
37,561
|
147 | 584 |
3.22B
3,224,536,728
|
| Delicious order |
13.0K
13,006
|
270 | 1,097 |
3.85B
3,852,247,140
|
| Capitalize |
37.5K
37,561
|
147 | 1,005 |
5.54B
5,549,074,335
|
| Tower of Hanoi |
37.5K
37,561
|
147 | 690 |
3.80B
3,809,812,230
|
COMPONENT LEVELS
| LEVEL | GATE | DELAY | ENERGY |
|---|---|---|---|
| NOT Gate |
1
|
1
|
1
|
| XOR Gate |
3
|
2
|
6
|
| Bigger OR Gate |
2
|
2
|
4
|
| Bigger AND Gate |
2
|
2
|
4
|
| XNOR Gate |
3
|
2
|
6
|
| Half Adder |
4
|
2
|
8
|
| Bit Inverter |
3
|
2
|
6
|
| Byte NOT |
8
|
1
|
8
|
| Byte NAND |
8
|
1
|
8
|
| Multiplexer |
33
|
2
|
66
|
| Saving Gracefully |
9
10
|
6
5
|
54
50
|
| Signed Negator |
31
|
5
|
155
|
| Saving Bytes |
65
73
|
6
5
|
390
365
|
| Counter |
95
98
|
14
10
|
1,330
980
|
| 1 Bit Decoder |
1
|
1
|
1
|
| 2 Bit Decoder |
4
|
2
|
8
|
| 3 Bit Decoder |
15
|
3
|
45
|
| Little Box |
340
372
|
7
5
|
2,380
1,860
|
| Arithmetic Logic Unit (ALU) 1 |
130
|
5
|
650
|
| Arithmetic Logic Unit (ALU) 2 |
366
|
67
|
24.5K
24,522
|
| Conditions |
26
|
9
|
234
|
| Punchcard Programming |
14.2K
14,256
|
83
|
1.18M
1,183,248
|
| Assembly Programming |
14.2K
14,256
|
83
|
1.18M
1,183,248
|
| Byte Constant |
0
|
0
|
0
|
| Byte XOR |
24
|
2
|
48
|
| Equality |
39
|
6
|
234
|
| Unsigned Less |
89
|
13
|
1,157
|
| LSR |
81
|
5
|
405
|
| ASR |
88
99
|
5
4
|
440
396
|
| One-hot Encoding |
75
|
7
|
525
|
| Objective Beauty |
22
23
24
25
|
8
7
6
5
|
176
161
144
125
|
