ARCHITECTURE LEVELS
| LEVEL | GATE | DELAY | CYCLE |
IPC
Instructions per cycle
|
ENERGY |
|---|---|---|---|---|---|
| Overture | 3,277 | 176 |
25.0K
25,000
|
1.00 |
14.4B
14,418,800,000
|
PROGRAMMING LEVELS
| LEVEL | GATE | DELAY | CYCLE | ENERGY |
|---|---|---|---|---|
| Nim |
1.82B
1,828,740,433
|
172 | 14 |
4.40T
4,403,606,962,664
|
| Random Number Generator |
1.82B
1,828,740,433
|
172 | 715 |
224T
224,898,498,450,340
|
| Delicious order |
1.82B
1,828,740,433
|
172 | 3,089 |
971T
971,624,421,976,364
|
| Capitalize |
1.82B
1,828,740,433
|
172 | 616 |
193T
193,758,706,357,216
|
COMPONENT LEVELS
| LEVEL | GATE | DELAY | ENERGY |
|---|---|---|---|
| NOT Gate |
1
|
1
|
1
|
| XOR Gate |
3
|
2
|
6
|
| Bigger OR Gate |
2
|
2
|
4
|
| Bigger AND Gate |
2
|
2
|
4
|
| XNOR Gate |
3
|
2
|
6
|
| Half Adder |
6
|
3
|
18
|
| Full Adder |
9
|
4
|
36
|
| Bit Inverter |
5
|
3
|
15
|
| Byte NOT |
8
|
1
|
8
|
| Byte NAND |
8
|
1
|
8
|
| Adding Bytes |
72
|
32
|
2,304
|
| Multiplexer |
33
|
2
|
66
|
| Saving Gracefully |
38
|
5
|
190
|
| Signed Negator |
80
|
33
|
2,640
|
| Saving Bytes |
304
|
5
|
1,520
|
| Counter |
145
|
37
|
5,365
|
| 1 Bit Decoder |
1
|
1
|
1
|
| 2 Bit Decoder |
6
|
2
|
12
|
| 3 Bit Decoder |
46
|
4
|
184
|
| Little Box |
1,372
|
7
|
9,604
|
| Arithmetic Logic Unit (ALU) 1 |
100
|
3
|
300
|
| Arithmetic Logic Unit (ALU) 2 |
614
|
98
|
60.1K
60,172
|
| Conditions |
73
|
6
|
438
|
| Byte Constant |
0
|
0
|
0
|
| Byte XOR |
40
|
3
|
120
|
| Equality |
311
|
102
|
31.7K
31,722
|
| Unsigned Less |
109
|
30
|
3,270
|
| Signed Less |
125
|
31
|
3,875
|
| LSR |
174
|
5
|
870
|
| Count leading zeroes |
1,037
|
39
|
40.4K
40,443
|
| ASR |
179
|
5
|
895
|
| One hot encoding |
174
|
5
|
870
|
| Comparison Flags |
2,284
|
124
|
283K
283,216
|
| Symphony ALU |
7,392
|
130
|
960K
960,960
|
| Condition Match |
11
|
5
|
55
|
| Objective beauty |
31
|
9
|
279
|
| Multiply |
1,986
|
231
|
458K
458,766
|
