ARCHITECTURE LEVELS
| LEVEL | GATE | DELAY | CYCLE |
IPC
Instructions per cycle
|
ENERGY |
|---|---|---|---|---|---|
| Overture |
14.5K
14,521
|
73 |
25.0K
25,000
|
1.00 |
26.5B
26,500,825,000
|
PROGRAMMING LEVELS
| LEVEL | GATE | DELAY | CYCLE | ENERGY |
|---|---|---|---|---|
| Nim |
1.82B
1,828,740,893
|
419 | 19 |
14.5T
14,558,606,249,173
|
| Random Number Generator |
1.82B
1,828,740,893
|
419 | 584 |
447T
447,485,581,553,528
|
| Delicious order |
1.82B
1,828,740,893
|
419 | 4,162 |
3,189T
3,189,101,011,003,054
|
| Capitalize |
1.82B
1,828,740,893
|
419 | 523 |
400T
400,744,793,069,341
|
| Tower of Hanoi |
1.82B
1,828,740,893
|
419 | 1,042 |
798T
798,424,616,402,014
|
COMPONENT LEVELS
| LEVEL | GATE | DELAY | ENERGY |
|---|---|---|---|
| NOT Gate |
1
|
1
|
1
|
| XOR Gate |
3
|
2
|
6
|
| Bigger OR Gate |
2
|
2
|
4
|
| Bigger AND Gate |
2
|
2
|
4
|
| XNOR Gate |
4
|
3
|
12
|
| Half Adder |
4
|
2
|
8
|
| Full Adder |
11
|
4
|
44
|
| Bit Inverter |
3
|
2
|
6
|
| Byte NOT |
8
|
1
|
8
|
| Byte NAND |
8
|
1
|
8
|
| Adding Bytes |
88
154
|
32
18
|
2,816
2,772
|
| Multiplexer |
33
|
2
|
66
|
| Saving Gracefully |
11
|
6
|
66
|
| Signed Negator |
96
|
33
|
3,168
|
| Saving Bytes |
88
|
6
|
528
|
| 1 Bit Decoder |
10
|
2
|
20
|
| 2 Bit Decoder |
16
|
6
|
96
|
| 3 Bit Decoder |
27
|
6
|
162
|
| Arithmetic Logic Unit (ALU) 1 |
148
|
4
|
592
|
| Arithmetic Logic Unit (ALU) 2 |
468
|
66
|
30.8K
30,888
|
| Byte XOR |
24
|
2
|
48
|
| Equality |
39
|
7
|
273
|
| Unsigned Less |
96
|
33
|
3,168
|
| Signed Less |
102
168
|
35
21
|
3,570
3,528
|
| LSR |
102
|
7
|
714
|
| Count leading zeroes |
532
|
137
|
72.8K
72,884
|
| ASR |
201
|
12
|
2,412
|
| One-hot Encoding |
150
|
13
|
1,950
|
| Comparison Flags |
1,045
|
72
|
75.2K
75,240
|
| Symphony ALU |
6,109
|
130
|
794K
794,170
|
| Condition Match |
11
|
5
|
55
|
| Objective Beauty |
30
|
8
|
240
|
| Multiply |
863
|
239
|
206K
206,257
|
