ARCHITECTURE LEVELS
| LEVEL | GATE | DELAY | CYCLE |
IPC
Instructions per cycle
|
ENERGY |
|---|---|---|---|---|---|
| Overture |
14.4K
14,430
|
88 |
25.0K
25,000
|
1.00 |
31.7B
31,746,000,000
|
PROGRAMMING LEVELS
| LEVEL | GATE | DELAY | CYCLE | ENERGY |
|---|---|---|---|---|
| Circumference |
14.4K
14,430
|
88 | 12 |
15.2M
15,238,080
|
| Mod 4 |
14.4K
14,430
|
88 | 5 |
6.34M
6,349,200
|
| Nim |
1.82B
1,828,738,439
|
173 | 33 |
10.4T
10,440,267,748,251
|
| Random Number Generator |
1.82B
1,828,738,439
|
173 | 584 |
184T
184,761,101,969,048
|
| Delicious order |
1.82B
1,828,738,439
|
173 | 3,297 |
1,043T
1,043,077,659,575,259
|
| Capitalize |
1.82B
1,828,738,439
|
173 | 1,783 |
564T
564,090,830,155,501
|
COMPONENT LEVELS
| LEVEL | GATE | DELAY | ENERGY |
|---|---|---|---|
| NOT Gate |
1
|
1
|
1
|
| XOR Gate |
3
|
2
|
6
|
| Bigger OR Gate |
3
|
2
|
6
|
| Bigger AND Gate |
3
|
2
|
6
|
| XNOR Gate |
4
|
3
|
12
|
| Half Adder |
4
|
2
|
8
|
| Full Adder |
9
|
4
|
36
|
| Bit Inverter |
3
|
2
|
6
|
| Byte NOT |
8
|
1
|
8
|
| Byte NAND |
8
|
1
|
8
|
| Adding Bytes |
72
|
32
|
2,304
|
| Multiplexer |
33
|
2
|
66
|
| Saving Gracefully |
10
|
5
|
50
|
| Signed Negator |
80
|
33
|
2,640
|
| Saving Bytes |
80
|
5
|
400
|
| Counter |
185
|
38
|
7,030
|
| 1 Bit Decoder |
1
|
1
|
1
|
| 2 Bit Decoder |
6
|
2
|
12
|
| 3 Bit Decoder |
48
|
6
|
288
|
| Little Box |
449
|
10
|
4,490
|
| Arithmetic Logic Unit (ALU) 1 |
130
|
5
|
650
|
| Arithmetic Logic Unit (ALU) 2 |
396
|
67
|
26.5K
26,532
|
| Conditions |
78
|
8
|
624
|
| Punchcard Programming |
14.4K
14,430
|
88
|
1.26M
1,269,840
|
| Assembly Programming |
14.4K
14,430
|
88
|
1.26M
1,269,840
|
| One-hot Encoding |
150
|
13
|
1,950
|
| Comparison Flags |
1,048
|
72
|
75.4K
75,456
|
| Symphony ALU |
5,615
|
137
|
769K
769,255
|
| Condition Match |
12
|
5
|
60
|
| Objective Beauty |
31
|
9
|
279
|
| Divide |
2,336
|
298
|
696K
696,128
|
| Modulo |
4,187
|
473
|
1.98M
1,980,451
|
| Multiply |
1,699
|
110
|
186K
186,890
|
