ARCHITECTURE LEVELS
| LEVEL | GATE | DELAY | CYCLE |
IPC
Instructions per cycle
|
ENERGY |
|---|---|---|---|---|---|
| Overture |
14.7K
14,784
|
62 |
17.9K
17,967
|
1.38 |
16.4B
16,468,695,936
|
PROGRAMMING LEVELS
| LEVEL | GATE | DELAY | CYCLE | ENERGY |
|---|---|---|---|---|
| Circumference | 2,543 | 44 | 9 |
1.00M
1,007,028
|
| Mod 4 | 0 | 0 | 1 | 0 |
| Code Breaker |
14.4K
14,422
|
86 | 1,280 |
1.58B
1,587,573,760
|
| The Maze |
14.2K
14,259
|
82 | 1,376 |
1.60B
1,608,871,488
|
| Random Number Generator |
14.9K
14,982
|
166 | 488 |
1.21B
1,213,661,856
|
| Delicious order |
1.82B
1,828,737,700
|
168 | 1,101 |
338T
338,257,954,893,600
|
| Capitalize | 2,518 | 60 | 472 |
71.3M
71,309,760
|
COMPONENT LEVELS
| LEVEL | GATE | DELAY | ENERGY |
|---|---|---|---|
| NOT Gate |
1
|
1
|
1
|
| XOR Gate |
3
|
2
|
6
|
| Bigger OR Gate |
2
|
2
|
4
|
| Bigger AND Gate |
2
|
2
|
4
|
| XNOR Gate |
3
|
2
|
6
|
| Half Adder |
4
|
2
|
8
|
| Byte NOT |
8
|
1
|
8
|
| Byte NAND |
8
|
1
|
8
|
| Adding Bytes |
56
80
|
32
14
|
1,792
1,120
|
| Multiplexer |
33
|
2
|
66
|
| Saving Gracefully |
10
|
5
|
50
|
| Saving Bytes |
65
73
|
6
5
|
390
365
|
| 1 Bit Decoder |
1
|
1
|
1
|
| 3 Bit Decoder |
20
|
3
|
60
|
| Arithmetic Logic Unit (ALU) 1 |
148
|
4
|
592
|
| Arithmetic Logic Unit (ALU) 2 |
213
237
|
38
20
|
8,094
4,740
|
| Punchcard Programming |
13.8K
13,831
|
28
|
387K
387,268
|
| Assembly Programming |
13.8K
13,831
|
28
|
387K
387,268
|
| Byte Constant |
0
|
0
|
0
|
| Byte XOR |
24
|
2
|
48
|
| Equality |
31
41
|
5
4
|
155
164
|
| Unsigned Less |
49
|
26
|
1,274
|
| Signed Less |
51
|
24
|
1,224
|
| LSR |
102
|
6
|
612
|
| Count leading zeroes |
272
|
16
|
4,352
|
| ASR |
102
|
6
|
612
|
| One-hot Encoding |
102
|
6
|
612
|
| Comparison Flags |
1,302
|
144
|
187K
187,488
|
| Condition Match |
11
|
6
|
66
|
| Divide |
1,368
|
280
|
383K
383,040
|
| Modulo |
1,369
|
282
|
386K
386,058
|
