ARCHITECTURE LEVELS
| LEVEL | GATE | DELAY | CYCLE |
IPC
Instructions per cycle
|
ENERGY |
|---|---|---|---|---|---|
| Overture |
14.3K
14,342
|
58 |
25.0K
25,000
|
1.00 |
20.7B
20,795,900,000
|
PROGRAMMING LEVELS
| LEVEL | GATE | DELAY | CYCLE | ENERGY |
|---|---|---|---|---|
| Code Breaker |
14.7K
14,732
|
83 | 1,799 |
2.19B
2,199,738,044
|
| Nim |
1.82B
1,828,738,720
|
188 | 15 |
5.15T
5,157,043,190,400
|
| Random Number Generator |
1.82B
1,828,738,720
|
188 | 520 |
178T
178,777,497,267,200
|
| Delicious order |
1.00B
1,006,655,136
|
188 | 1,638 |
309T
309,993,409,200,384
|
| Capitalize |
1.82B
1,828,738,720
|
188 | 574 |
197T
197,342,852,752,640
|
COMPONENT LEVELS
| LEVEL | GATE | DELAY | ENERGY |
|---|---|---|---|
| NOT Gate |
1
|
1
|
1
|
| XOR Gate |
3
|
2
|
6
|
| Bigger OR Gate |
2
|
2
|
4
|
| Bigger AND Gate |
2
|
2
|
4
|
| XNOR Gate |
3
|
2
|
6
|
| Half Adder |
5
|
3
|
15
|
| Full Adder |
11
|
6
|
66
|
| Bit Inverter |
3
|
2
|
6
|
| Adding Bytes |
72
|
32
|
2,304
|
| Signed Negator |
27
|
8
|
216
|
| Counter |
186
|
39
|
7,254
|
| Arithmetic Logic Unit (ALU) 2 |
308
|
34
|
10.4K
10,472
|
| Conditions |
49
|
7
|
343
|
| LSR |
150
|
12
|
1,800
|
| ASR |
152
|
13
|
1,976
|
| One-hot Encoding |
150
|
12
|
1,800
|
| Comparison Flags |
1,080
|
72
|
77.7K
77,760
|
| Symphony ALU |
6,109
6,634
|
214
130
|
1.30M
1,307,326
862K
862,420
|
| Divide |
2,315
|
940
|
2.17M
2,176,100
|
| Multiply |
1,066
|
379
|
404K
404,014
|
