ARCHITECTURE LEVELS
| LEVEL | GATE | DELAY | CYCLE |
IPC
Instructions per cycle
|
ENERGY |
|---|---|---|---|---|---|
| Overture |
14.5K
14,546
|
49 |
25.0K
25,000
|
1.00 |
17.8B
17,818,850,000
|
PROGRAMMING LEVELS
| LEVEL | GATE | DELAY | CYCLE | ENERGY |
|---|---|---|---|---|
| Mod 4 |
14.6K
14,665
|
83 | 5 |
6.08M
6,085,975
|
| Code Breaker |
14.6K
14,665
|
83 | 1,792 |
2.18B
2,181,213,440
|
| The Maze |
14.6K
14,665
|
83 | 3,360 |
4.08B
4,089,775,200
|
| Nim |
1.82B
1,828,736,462
|
173 | 23 |
7.27T
7,276,542,382,298
|
| Random Number Generator |
1.82B
1,828,736,462
|
173 | 520 |
164T
164,513,132,121,520
|
| Delicious order |
1.82B
1,828,736,462
|
173 | 1,962 |
620T
620,720,702,350,812
|
| Capitalize |
1.82B
1,828,736,462
|
173 | 948 |
299T
299,920,094,713,848
|
| Tower of Hanoi |
1.82B
1,828,736,462
|
173 | 1,443 |
456T
456,523,941,637,218
|
COMPONENT LEVELS
| LEVEL | GATE | DELAY | ENERGY |
|---|---|---|---|
| NOT Gate |
1
|
1
|
1
|
| XOR Gate |
3
|
2
|
6
|
| Bigger OR Gate |
2
|
2
|
4
|
| Bigger AND Gate |
2
|
2
|
4
|
| XNOR Gate |
5
|
4
|
20
|
| Half Adder |
5
|
3
|
15
|
| Full Adder |
9
|
4
|
36
|
| Adding Bytes |
72
|
32
|
2,304
|
| Multiplexer |
33
|
2
|
66
|
| Signed Negator |
37
|
9
|
333
|
| 1 Bit Decoder |
1
|
1
|
1
|
| Conditions |
47
|
8
|
376
|
| Byte Constant |
0
|
0
|
0
|
| Byte XOR |
40
|
3
|
120
|
| Equality |
39
|
8
|
312
|
| Unsigned Less |
81
|
34
|
2,754
|
| Signed Less |
91
|
35
|
3,185
|
| LSR |
99
|
4
|
396
|
| Count leading zeroes |
400
|
32
|
12.8K
12,800
|
| ASR |
99
|
4
|
396
|
| One-hot Encoding |
99
|
4
|
396
|
| Comparison Flags |
921
|
140
|
128K
128,940
|
| Symphony ALU |
4,478
|
141
|
631K
631,398
|
| Condition Match |
10
|
6
|
60
|
| Objective Beauty |
29
|
8
|
232
|
| Multiply |
768
|
226
|
173K
173,568
|
