ARCHITECTURE LEVELS
| LEVEL | GATE | DELAY | CYCLE |
IPC
Instructions per cycle
|
ENERGY |
|---|---|---|---|---|---|
| Overture |
14.4K
14,412
|
71 |
25.0K
25,000
|
1.00 |
25.5B
25,581,300,000
|
PROGRAMMING LEVELS
| LEVEL | GATE | DELAY | CYCLE | ENERGY |
|---|---|---|---|---|
| Circumference |
14.4K
14,484
|
103 | 13 |
19.3M
19,394,076
|
| Mod 4 |
14.4K
14,484
|
103 | 5 |
7.45M
7,459,260
|
| Code Breaker |
14.4K
14,484
|
103 | 2,233 |
3.33B
3,331,305,516
|
| The Maze |
14.4K
14,484
|
103 |
30.8K
30,862
|
46.0B
46,041,536,424
|
COMPONENT LEVELS
| LEVEL | GATE | DELAY | ENERGY |
|---|---|---|---|
| NOT Gate |
1
|
1
|
1
|
| XOR Gate |
3
|
2
|
6
|
| Bigger OR Gate |
3
|
2
|
6
|
| Bigger AND Gate |
3
|
2
|
6
|
| XNOR Gate |
4
|
3
|
12
|
| Half Adder |
5
|
3
|
15
|
| Full Adder |
11
12
|
6
4
|
66
48
|
| Bit Inverter |
4
|
3
|
12
|
| Byte NOT |
8
|
1
|
8
|
| Byte NAND |
8
|
1
|
8
|
| Adding Bytes |
72
73
|
18
17
|
1,296
1,241
|
| Multiplexer |
33
|
2
|
66
|
| Saving Gracefully |
10
|
5
|
50
|
| Signed Negator |
80
|
19
|
1,520
|
| Saving Bytes |
80
|
5
|
400
|
| Counter |
225
|
54
|
12.1K
12,150
|
| 1 Bit Decoder |
1
|
1
|
1
|
| 2 Bit Decoder |
6
|
2
|
12
|
| 3 Bit Decoder |
36
|
4
|
144
|
| Little Box |
396
|
6
|
2,376
|
| Arithmetic Logic Unit (ALU) 1 |
110
|
3
|
330
|
| Arithmetic Logic Unit (ALU) 2 |
508
|
98
|
49.7K
49,784
|
| Conditions |
70
|
6
|
420
|
| Punchcard Programming |
14.4K
14,484
|
103
|
1.49M
1,491,852
|
| Assembly Programming |
14.4K
14,484
|
103
|
1.49M
1,491,852
|
| Byte Constant |
0
|
0
|
0
|
| Byte XOR |
32
|
3
|
96
|
| Equality |
50
|
8
|
400
|
| Unsigned Less |
80
|
19
|
1,520
|
| Signed Less |
79
|
20
|
1,580
|
| LSR |
99
|
6
|
594
|
| Count leading zeroes |
264
|
16
|
4,224
|
| ASR |
99
|
6
|
594
|
| One-hot Encoding |
99
|
6
|
594
|
| Comparison Flags |
1,599
|
416
|
665K
665,184
|
| Symphony ALU |
4,488
|
81
|
363K
363,528
|
| Condition Match |
40
|
6
|
240
|
| Objective Beauty |
32
|
9
|
288
|
| Multiply |
1,325
|
133
|
176K
176,225
|
