ARCHITECTURE LEVELS
| LEVEL | GATE | DELAY | CYCLE |
IPC
Instructions per cycle
|
ENERGY |
|---|---|---|---|---|---|
| Overture |
14.4K
14,484
|
55 |
25.0K
25,000
|
1.00 |
19.9B
19,915,500,000
|
COMPONENT LEVELS
| LEVEL | GATE | DELAY | ENERGY |
|---|---|---|---|
| NOT Gate |
1
|
1
|
1
|
| XOR Gate |
3
|
2
|
6
|
| Bigger OR Gate |
2
|
2
|
4
|
| Bigger AND Gate |
2
|
2
|
4
|
| XNOR Gate |
6
|
4
|
24
|
| Adding Bytes |
72
|
17
|
1,224
|
| Multiplexer |
33
|
2
|
66
|
| Signed Negator |
80
|
18
|
1,440
|
| Byte XOR |
24
|
2
|
48
|
| Signed Less |
118
|
20
|
2,360
|
| Multiply |
904
|
55
|
49.7K
49,720
|
