ARCHITECTURE LEVELS
| LEVEL | GATE | DELAY | CYCLE |
IPC
Instructions per cycle
|
ENERGY |
|---|---|---|---|---|---|
| Overture | 2,093 | 34 |
28.5K
28,587
|
0.87 |
2.03B
2,034,308,094
|
PROGRAMMING LEVELS
| LEVEL | GATE | DELAY | CYCLE | ENERGY |
|---|---|---|---|---|
| Circumference |
14.4K
14,412
|
72 | 9 |
9.33M
9,338,976
|
| Mod 4 |
14.4K
14,444
|
72 | 5 |
5.19M
5,199,840
|
| Code Breaker |
14.4K
14,444
|
72 | 157 |
163M
163,274,976
|
| The Maze |
14.4K
14,444
|
72 | 2,064 |
2.14B
2,146,493,952
|
COMPONENT LEVELS
| LEVEL | GATE | DELAY | ENERGY |
|---|---|---|---|
| NOT Gate |
1
|
1
|
1
|
| XOR Gate |
3
|
2
|
6
|
| Bigger OR Gate |
2
|
2
|
4
|
| Bigger AND Gate |
2
|
2
|
4
|
| XNOR Gate |
3
|
2
|
6
|
| Half Adder |
4
|
2
|
8
|
| Full Adder |
9
|
4
|
36
|
| Bit Inverter |
3
|
2
|
6
|
| Byte NOT |
8
|
1
|
8
|
| Byte NAND |
8
|
1
|
8
|
| Adding Bytes |
80
140
|
19
15
|
1,520
2,100
|
| Multiplexer |
33
|
2
|
66
|
| Saving Gracefully |
10
|
5
|
50
|
| Signed Negator |
96
104
|
33
20
|
3,168
2,080
|
| Saving Bytes |
80
|
5
|
400
|
| Counter |
101
|
14
|
1,414
|
| 1 Bit Decoder |
1
|
1
|
1
|
| 2 Bit Decoder |
6
|
2
|
12
|
| 3 Bit Decoder |
22
|
4
|
88
|
| Little Box |
412
|
7
|
2,884
|
| Arithmetic Logic Unit (ALU) 1 |
148
|
4
|
592
|
| Arithmetic Logic Unit (ALU) 2 |
366
|
21
|
7,686
|
| Conditions |
49
|
8
|
392
|
| Punchcard Programming |
14.4K
14,412
|
72
|
1.03M
1,037,664
|
| Assembly Programming |
14.4K
14,412
|
72
|
1.03M
1,037,664
|
| Byte Constant |
0
|
0
|
0
|
| Byte XOR |
24
|
2
|
48
|
| Equality |
39
|
7
|
273
|
| Unsigned Less |
97
|
34
|
3,298
|
| Signed Less |
99
|
35
|
3,465
|
| LSR |
99
|
6
|
594
|
| Count leading zeroes |
264
|
16
|
4,224
|
| ASR |
101
|
7
|
707
|
| One-hot Encoding |
99
|
6
|
594
|
| Comparison Flags |
1,028
|
140
|
143K
143,920
|
| Symphony ALU |
4,982
|
141
|
702K
702,462
|
| Condition Match |
27
|
9
|
243
|
| Objective Beauty |
28
|
8
|
224
|
| Multiply |
744
|
97
|
72.1K
72,168
|
