ARCHITECTURE LEVELS
| LEVEL | GATE | DELAY | CYCLE |
IPC
Instructions per cycle
|
ENERGY |
|---|---|---|---|---|---|
| Overture |
14.4K
14,466
|
61 |
25.0K
25,000
|
1.00 |
22.0B
22,060,650,000
|
PROGRAMMING LEVELS
| LEVEL | GATE | DELAY | CYCLE | ENERGY |
|---|---|---|---|---|
| Circumference |
14.6K
14,652
|
165 | 9 |
21.7M
21,758,220
|
| Mod 4 |
14.5K
14,588
|
149 | 5 |
10.8M
10,868,060
|
| Code Breaker |
14.6K
14,652
|
165 | 1,278 |
3.08B
3,089,667,240
|
| The Maze |
14.5K
14,588
|
149 | 1,673 |
3.63B
3,636,452,876
|
COMPONENT LEVELS
| LEVEL | GATE | DELAY | ENERGY |
|---|---|---|---|
| NOT Gate |
2
|
1
|
2
|
| XOR Gate |
3
|
2
|
6
|
| Bigger OR Gate |
2
|
2
|
4
|
| Bigger AND Gate |
2
|
2
|
4
|
| XNOR Gate |
3
|
2
|
6
|
| Half Adder |
4
|
2
|
8
|
| Full Adder |
9
|
4
|
36
|
| Byte NOT |
16
|
1
|
16
|
| Byte NAND |
8
|
1
|
8
|
| Adding Bytes |
72
|
32
|
2,304
|
| Saving Gracefully |
10
|
5
|
50
|
| Saving Bytes |
80
|
5
|
400
|
| Counter |
144
|
14
|
2,016
|
| 1 Bit Decoder |
2
|
1
|
2
|
| 2 Bit Decoder |
12
|
2
|
24
|
| 3 Bit Decoder |
38
|
4
|
152
|
| Little Box |
396
|
6
|
2,376
|
| Arithmetic Logic Unit (ALU) 1 |
148
|
4
|
592
|
| Arithmetic Logic Unit (ALU) 2 |
534
|
98
|
52.3K
52,332
|
| Conditions |
72
|
5
|
360
|
| Punchcard Programming |
14.6K
14,652
|
165
|
2.41M
2,417,580
|
| Assembly Programming |
14.6K
14,652
|
165
|
2.41M
2,417,580
|
| Byte Constant |
0
|
0
|
0
|
| Byte XOR |
32
|
3
|
96
|
| Equality |
39
|
6
|
234
|
| Unsigned Less |
66
|
8
|
528
|
| LSR |
150
|
12
|
1,800
|
| Count leading zeroes |
187
|
9
|
1,683
|
| ASR |
350
|
16
|
5,600
|
| One-hot Encoding |
150
|
12
|
1,800
|
| Comparison Flags |
1,090
|
72
|
78.4K
78,480
|
| Symphony ALU |
7,360
|
130
|
956K
956,800
|
| Condition Match |
9
|
6
|
54
|
| Objective Beauty |
30
|
8
|
240
|
| Divide |
2,281
2,969
|
500
440
|
1.14M
1,140,500
1.30M
1,306,360
|
| Modulo |
2,281
|
508
|
1.15M
1,158,748
|
| Multiply |
2,178
|
352
|
766K
766,656
|
