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ARCHITECTURE LEVELS

LEVEL GATE DELAY CYCLE
IPC Instructions per cycle
ENERGY
Overture 2,090 254
25.0K 25,000
1.00
13.2B 13,271,500,000

PROGRAMMING LEVELS

LEVEL GATE DELAY CYCLE ENERGY
Circumference
14.6K 14,634
135 12
23.7M 23,707,080
Mod 4
14.6K 14,634
135 5
9.87M 9,877,950
The Maze
14.6K 14,634
135 1,991
3.93B 3,933,399,690
Random Number Generator
1.82B 1,828,738,413
236 520
224T 224,422,778,043,360

COMPONENT LEVELS

LEVEL GATE DELAY ENERGY
NOT Gate
1
1
1
XOR Gate
4
3
12
Bigger OR Gate
2
2
4
Bigger AND Gate
2
2
4
XNOR Gate
5
4
20
Half Adder
4
3
12
Full Adder
9
6
54
Bit Inverter
4
3
12
Byte NOT
8
1
8
Byte NAND
8
1
8
Adding Bytes
72
48
3,456
Arithmetic Logic Unit (ALU) 1
148
4
592
Arithmetic Logic Unit (ALU) 2
390
104
40.5K 40,560
Conditions
66
11
726
Assembly Programming
14.6K 14,634
135
1.97M 1,975,590
Symphony ALU
6,339
389
2.46M 2,465,871
Condition Match
9
6
54
Divide
15.6K 15,698
1,722
27.0M 27,031,956
Modulo
14.7K 14,719
1,745
25.6M 25,684,655
Multiply
1,682
350
588K 588,700