| LEVEL | GATE | DELAY | CYCLE | ENERGY |
|---|---|---|---|---|
| Delicious order |
51.3K
51,377
|
994 | 34 |
1.73B
1,736,337,092
|
| LEVEL | GATE | DELAY | ENERGY |
|---|---|---|---|
| NOT Gate |
1
|
1
|
1
|
| XOR Gate |
3
|
2
|
6
|
| Bigger OR Gate |
6
|
3
|
18
|
| Bigger AND Gate |
6
|
3
|
18
|
| XNOR Gate |
4
|
3
|
12
|
| Half Adder |
5
|
3
|
15
|
| Full Adder |
9
|
4
|
36
|
| Bit Inverter |
3
|
2
|
6
|
| Arithmetic Logic Unit (ALU) 2 |
496
|
76
|
37.6K
37,696
|
| Assembly Programming |
14.7K
14,760
|
86
|
1.26M
1,269,360
|
| Objective beauty |
29
|
7
|
203
|
| Divide |
1,031
|
249
|
256K
256,719
|
| Modulo |
1,676
|
396
|
663K
663,696
|
| Multiply |
564
|
151
|
85.1K
85,164
|