COMPLETED ARCHITECTURE LEVELS
| LEVEL | GATE | DELAY | TICK | ENERGY |
|---|---|---|---|---|
| Circumference |
14.6K
14,604
|
121 | 15 |
26.5M
26,506,260
|
| Mod 4 |
14.6K
14,604
|
121 | 5 |
8.83M
8,835,420
|
COMPLETED LEVELS
| LEVEL | GATE | DELAY | ENERGY |
|---|---|---|---|
| NOT Gate |
1
|
1
|
1
|
| XOR Gate |
4
|
3
|
12
|
| Bigger OR Gate |
2
|
2
|
4
|
| Bigger AND Gate |
2
|
2
|
4
|
| XNOR Gate |
5
|
4
|
20
|
| Half Adder |
5
|
3
|
15
|
| Full Adder |
11
|
6
|
66
|
| Bit inverter |
4
|
3
|
12
|
| Byte NOT |
8
|
1
|
8
|
| Byte NAND |
8
|
1
|
8
|
| Multiplexer |
33
|
2
|
66
|
| Saving Gracefully |
10
|
5
|
50
|
| Signed Negator |
108
|
51
|
5,508
|
| Saving Bytes |
80
|
5
|
400
|
| Counter |
213
|
57
|
12.1K
12,141
|
| 1 Bit Decoder |
1
|
1
|
1
|
| 2 Bit Decoder |
8
|
4
|
32
|
| 3 Bit Decoder |
37
|
4
|
148
|
| Little Box |
412
|
7
|
2,884
|
| Arithmetic Logic Unit (ALU) 1 |
106
|
6
|
636
|
| Arithmetic Logic Unit (ALU) 2 |
380
|
105
|
39.9K
39,900
|
| Conditions |
120
|
56
|
6,720
|
| Punchcard Programming |
14.6K
14,604
|
121
|
1.76M
1,767,084
|
