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Vorag
COMPLETE 56%

COMPLETED ARCHITECTURE LEVELS

LEVEL GATE DELAY TICK ENERGY
Circumference
14.4K 14,410
72 9
9.33M 9,337,680

COMPLETED LEVELS

LEVEL GATE DELAY ENERGY
NOT Gate
1
1
1
XOR Gate
3
2
6
Bigger OR Gate
2
2
4
Bigger AND Gate
2
2
4
XNOR Gate
3
2
6
Half Adder
4
2
8
Full Adder
9
4
36
Bit inverter
3
2
6
Byte NOT
8
1
8
Byte NAND
8
1
8
Adding Bytes
72
32
2,304
Multiplexer
33
2
66
Saving Gracefully
10
5
50
Signed Negator
80
33
2,640
Saving Bytes
80
5
400
Counter
185
38
7,030
1 Bit Decoder
1
1
1
2 Bit Decoder
6
2
12
3 Bit Decoder
35
4
140
Little Box
492
7
3,444
Arithmetic Logic Unit (ALU) 1
116
4
464
Arithmetic Logic Unit (ALU) 2
403
66
26.5K 26,598
Conditions
62
7
434
Punchcard Programming
14.4K 14,410
72
1.03M 1,037,520
Assembly Programming
14.4K 14,410
72
1.03M 1,037,520