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ARCHITECTURE LEVELS

LEVEL GATE DELAY CYCLE
IPC Instructions per cycle
ENERGY
Overture 1,927 18
41.2K 41,215
0.60
1.42B 1,429,583,490

PROGRAMMING LEVELS

LEVEL GATE DELAY CYCLE ENERGY
Circumference
14.4K 14,454
66 9
8.58M 8,585,676
Mod 4 0 0 1 0
The Maze
14.3K 14,322
83 2,437
2.89B 2,896,925,262

COMPONENT LEVELS

LEVEL GATE DELAY ENERGY
NOT Gate
1
1
1
XOR Gate
3
2
6
Bigger OR Gate
2
2
4
Bigger AND Gate
2
2
4
XNOR Gate
3
2
6
Full Adder
7
4
28
Bit Inverter
3
2
6
Adding Bytes
56
80
32
11
1,792
880
Multiplexer
33
2
66
Counter
129
153
37
16
4,773
2,448
Arithmetic Logic Unit (ALU) 2
288
41
11.8K 11,808
Conditions
20
6
120
Count leading zeroes
24
5
120
Comparison Flags
1,080
72
77.7K 77,760
Symphony ALU
5,761
203
1.16M 1,169,483
Objective beauty
22
8
176
Modulo
2,215
209
462K 462,935