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Lorenaga
COMPLETE 56%

COMPLETED ARCHITECTURE LEVELS

LEVEL GATE DELAY TICK ENERGY
Circumference
14.3K 14,343
86 13
16.0M 16,035,474

COMPLETED LEVELS

LEVEL GATE DELAY ENERGY
NOT Gate
1
1
1
XOR Gate
3
2
6
Bigger OR Gate
2
2
4
Bigger AND Gate
2
2
4
XNOR Gate
3
2
6
Half Adder
4
2
8
Full Adder
11
4
44
Byte NOT
8
1
8
Byte NAND
8
1
8
Adding Bytes
88
32
2,816
Multiplexer
33
2
66
Saving Gracefully
10
5
50
Signed Negator
96
33
3,168
Saving Bytes
80
5
400
Counter
169
37
6,253
1 Bit Decoder
1
1
1
2 Bit Decoder
6
2
12
3 Bit Decoder
22
4
88
Little Box
396
6
2,376
Arithmetic Logic Unit (ALU) 1
137
148
9
4
1,233
592
Arithmetic Logic Unit (ALU) 2
403
494
67
66
27.0K 27,001
32.6K 32,604
Conditions
50
8
400
Punchcard Programming
14.3K 14,343
86
1.23M 1,233,498
Assembly Programming
14.3K 14,343
86
1.23M 1,233,498