ARCHITECTURE LEVELS
| LEVEL | GATE | DELAY | CYCLE |
IPC
Instructions per cycle
|
ENERGY |
|---|---|---|---|---|---|
| Overture |
14.1K
14,149
|
84 |
25.0K
25,000
|
1.00 |
29.7B
29,712,900,000
|
PROGRAMMING LEVELS
| LEVEL | GATE | DELAY | CYCLE | ENERGY |
|---|---|---|---|---|
| Nim | 4 | 2 | 3 | 24 |
| Capitalize | 5 | 4 | 112 | 2,240 |
COMPONENT LEVELS
| LEVEL | GATE | DELAY | ENERGY |
|---|---|---|---|
| NOT Gate |
1
|
1
|
1
|
| XOR Gate |
3
|
2
|
6
|
| Bigger OR Gate |
2
|
2
|
4
|
| Bigger AND Gate |
2
|
2
|
4
|
| XNOR Gate |
3
|
2
|
6
|
| Half Adder |
3
|
2
|
6
|
| Full Adder |
10
|
4
|
40
|
| Bit Inverter |
3
|
2
|
6
|
| Byte NOT |
8
|
1
|
8
|
| Byte NAND |
8
|
1
|
8
|
| Adding Bytes |
80
|
32
|
2,560
|
| Multiplexer |
33
|
2
|
66
|
| Saving Gracefully |
10
|
5
|
50
|
| Signed Negator |
21
|
8
|
168
|
| 1 Bit Decoder |
1
|
1
|
1
|
| 3 Bit Decoder |
27
|
6
|
162
|
| Arithmetic Logic Unit (ALU) 1 |
131
|
7
|
917
|
| Arithmetic Logic Unit (ALU) 2 |
244
|
37
|
9,028
|
| Conditions |
26
|
5
|
130
|
| Byte Constant |
0
|
0
|
0
|
| Byte XOR |
24
|
2
|
48
|
| Equality |
41
|
4
|
164
|
| LSR |
99
|
6
|
594
|
| ASR |
99
|
6
|
594
|
| One-hot Encoding |
99
|
6
|
594
|
| Objective Beauty |
22
|
8
|
176
|
| Modulo |
1,704
|
319
|
543K
543,576
|
| Multiply |
688
|
97
|
66.7K
66,736
|
