ARCHITECTURE LEVELS
| LEVEL | GATE | DELAY | CYCLE |
IPC
Instructions per cycle
|
ENERGY |
|---|---|---|---|---|---|
| Overture |
14.2K
14,263
|
49 |
25.0K
25,000
|
1.00 |
17.4B
17,472,175,000
|
PROGRAMMING LEVELS
| LEVEL | GATE | DELAY | CYCLE | ENERGY |
|---|---|---|---|---|
| Circumference | 520 | 225 | 1 |
117K
117,000
|
| Mod 4 |
14.3K
14,326
|
62 | 5 |
4.44M
4,441,060
|
| Code Breaker |
14.5K
14,558
|
166 | 1,279 |
3.09B
3,090,867,212
|
| The Maze |
14.5K
14,558
|
166 | 2,140 |
5.17B
5,171,583,920
|
| Nim |
1.82B
1,828,730,179
|
169 | 13 |
4.01T
4,017,720,203,263
|
| Random Number Generator | 4,476 | 111 | 65 |
32.2M
32,294,340
|
| Delicious order |
1.82B
1,828,730,179
|
169 | 2,097 |
648T
648,089,174,326,347
|
| Capitalize |
1.82B
1,828,730,179
|
169 | 523 |
161T
161,635,974,331,273
|
| Tower of Hanoi |
1.82B
1,828,730,190
|
170 | 986 |
306T
306,531,754,447,800
|
COMPONENT LEVELS
| LEVEL | GATE | DELAY | ENERGY |
|---|---|---|---|
| NOT Gate |
1
|
1
|
1
|
| XOR Gate |
3
|
2
|
6
|
| Bigger AND Gate |
2
|
2
|
4
|
| XNOR Gate |
3
|
2
|
6
|
| Half Adder |
3
|
2
|
6
|
| Full Adder |
7
|
4
|
28
|
| Bit Inverter |
3
|
2
|
6
|
| Adding Bytes |
56
|
32
|
1,792
|
| Saving Gracefully |
10
|
5
|
50
|
| Signed Negator |
32
|
10
|
320
|
| Saving Bytes |
73
|
6
|
438
|
| Counter |
137
|
16
|
2,192
|
| 2 Bit Decoder |
4
|
2
|
8
|
| 3 Bit Decoder |
30
|
4
|
120
|
| Little Box |
376
|
7
|
2,632
|
| Conditions |
64
|
8
|
512
|
| Punchcard Programming |
14.2K
14,266
|
62
|
884K
884,492
|
| Assembly Programming |
14.5K
14,558
|
166
|
2.41M
2,416,628
|
| Byte Constant |
0
|
0
|
0
|
| Unsigned Less |
80
|
33
|
2,640
|
| Signed Less |
86
|
35
|
3,010
|
| LSR |
158
|
5
|
790
|
| Count leading zeroes |
159
|
12
|
1,908
|
| One hot encoding |
150
158
|
13
5
|
1,950
790
|
| Symphony ALU |
5,642
|
141
|
795K
795,522
|
| Condition Match |
8
|
5
|
40
|
| Objective beauty |
24
|
9
|
216
|
| Divide |
2,758
|
551
|
1.51M
1,519,658
|
| Multiply |
520
|
225
|
117K
117,000
|
