COMPLETED ARCHITECTURE LEVELS
| LEVEL | GATE | DELAY | TICK | ENERGY |
|---|---|---|---|---|
| The Maze |
14.7K
14,715
|
83 | 2,628 |
3.20B
3,209,694,660
|
COMPLETED LEVELS
| LEVEL | GATE | DELAY | ENERGY |
|---|---|---|---|
| XOR Gate |
3
|
2
|
6
|
| Bigger OR Gate |
2
|
2
|
4
|
| Bigger AND Gate |
2
|
2
|
4
|
| XNOR Gate |
3
|
2
|
6
|
| Half Adder |
3
|
2
|
6
|
| Full Adder |
7
|
4
|
28
|
| Byte NOT |
8
|
1
|
8
|
| Byte NAND |
8
|
1
|
8
|
| Adding Bytes |
56
|
32
|
1,792
|
| Multiplexer |
33
|
2
|
66
|
| Saving Gracefully |
10
|
5
|
50
|
| Signed Negator |
64
|
33
|
2,112
|
| Saving Bytes |
80
|
5
|
400
|
| Counter |
129
|
37
|
4,773
|
| 1 Bit Decoder |
1
|
1
|
1
|
| 2 Bit Decoder |
6
|
2
|
12
|
| 3 Bit Decoder |
54
|
5
|
270
|
| Little Box |
494
|
7
|
3,458
|
| Arithmetic Logic Unit (ALU) 1 |
116
|
4
|
464
|
| Symphony ALU |
6,324
|
301
|
1.90M
1,903,524
|
| Condition Match |
58
|
15
|
870
|
| Score |
22
|
8
|
176
|
| Multiply |
520
|
225
|
117K
117,000
|
| Divide |
705K
705,339
|
40.6K
40,631
|
28.6B
28,658,628,909
|
| Modulo |
11.3M
11,319,044
|
164K
164,455
|
1.86T
1,861,473,381,020
|
