ARCHITECTURE LEVELS
| LEVEL | GATE | DELAY | CYCLE |
IPC
Instructions per cycle
|
ENERGY |
|---|---|---|---|---|---|
| Overture |
14.7K
14,736
|
88 |
25.0K
25,000
|
1.00 |
32.4B
32,419,200,000
|
PROGRAMMING LEVELS
| LEVEL | GATE | DELAY | CYCLE | ENERGY |
|---|---|---|---|---|
| Circumference |
14.7K
14,768
|
104 | 13 |
19.9M
19,966,336
|
| Mod 4 |
14.7K
14,768
|
104 | 5 |
7.67M
7,679,360
|
| Code Breaker |
14.7K
14,768
|
104 | 3,792 |
5.82B
5,824,026,624
|
| The Maze |
14.7K
14,768
|
104 | 2,336 |
3.58B
3,587,796,992
|
COMPONENT LEVELS
| LEVEL | GATE | DELAY | ENERGY |
|---|---|---|---|
| NOT Gate |
1
|
1
|
1
|
| XOR Gate |
4
|
3
|
12
|
| Bigger OR Gate |
2
|
2
|
4
|
| Bigger AND Gate |
2
|
2
|
4
|
| XNOR Gate |
4
|
3
|
12
|
| Half Adder |
5
|
3
|
15
|
| Adding Bytes |
190
|
17
|
3,230
|
| Multiplexer |
33
|
2
|
66
|
| Saving Gracefully |
10
|
5
|
50
|
| Signed Negator |
112
|
49
|
5,488
|
| Saving Bytes |
80
|
5
|
400
|
| 1 Bit Decoder |
1
|
1
|
1
|
| 2 Bit Decoder |
6
|
2
|
12
|
| Arithmetic Logic Unit (ALU) 2 |
507
|
98
|
49.6K
49,686
|
| Conditions |
101
|
7
|
707
|
| Punchcard Programming |
14.7K
14,768
|
104
|
1.53M
1,535,872
|
| Byte Constant |
0
|
0
|
0
|
| Byte XOR |
32
|
3
|
96
|
| Unsigned Less |
77
|
16
|
1,232
|
| Signed Less |
85
|
18
|
1,530
|
| LSR |
99
|
6
|
594
|
| Count leading zeroes |
264
|
16
|
4,224
|
| ASR |
233
|
7
|
1,631
|
| One-hot Encoding |
99
|
6
|
594
|
| Comparison Flags |
912
|
72
|
65.6K
65,664
|
| Symphony ALU |
5,495
|
130
|
714K
714,350
|
| Divide |
1,835
|
303
|
556K
556,005
|
| Modulo |
1,835
|
307
|
563K
563,345
|
| Multiply |
992
|
338
|
335K
335,296
|
